1. Field of the Invention
The present invention relates to a storage control apparatus provided therein with a memory device being a combination of a cache memory of a storage device with a system memory on the side of a Central Processing Unit to remain reliable at the time of data input/output control.
2. Description of the Related Art
There is a technology of making use of a plurality of memories, e.g., disk memories and cache memories, for control over data input/output to/from a storage device provided therein with a plurality of disk drives. As such a technology, Patent Document 1 (JP-A-59-135563) describes, for example, a computer system in which a disk/cache device to be connected to a disk control device is configured by a portion of nonvolatile memory and a portion of volatile memory. With such a computer system, an output process from a Central Processing Unit (CPU) is completed when data writing to the nonvolatile portion in the disk/cache device is finished, and a plurality of data pieces on the nonvolatile portion in the disk/cache device are collectively written into the disk drives.
Patent Document 2 (JP-A-2000-347815) describes, for example, a disk array system in which, for increasing the reliability of the disk array system, a integrity code is added to data on a logical data block basis for writing into a disk drive, thereby detecting any reading/writing with respect to any abnormal address of split data or detecting any data bit error during data transfer. The integrity code is of any Logical Address or of exclusive OR LRC (Longitudinal Redundancy Check).
FIGS. 19 to 21 show, respectively, configuration diagrams of first and second previous examples, i.e., storage control apparatus provided therein with a memory device being a combination of a cache memory and a system memory on the CPU side, and exemplary dual write of data in the first previous example.
In the storage control apparatus of the first previous example of FIG. 19, dual write of data is performed using a dual path through a connection of a Peripheral Component Interconnect Express (PCIe) 209 to a memory control hub (MCH) 203. The memory control hub 203 is being connected with a battery-backed-up memory (Memory) 201, a Central Processing Unit (CPU) 202, a front-end chip (FE) 204, and a back-end chip (BE) 206. The battery-backed-up memory 201 is a combination of a CS/DS (Code Storage/Data Storage) memory being a system memory on the side of the CPU, and a cache (Cache) memory of a storage device.
In the storage control apparatus of the second previous example of FIG. 20, dual write of data is performed using a dual path (Dual Path) by an application-specific integrated circuit (ASIC) 207 connected to the memory control hub (MCH) 203, and various other components, i.e., the front-end chip (FE) 204, the back-end chip (BE) 206, and the battery-backed-up cache memory (Cache Memory) 201. The memory control hub 203 is being connected to a cache (Cache) memory 210 of a storage device and the Central Processing Unit (CPU) 202, and the cache memory 201 is being a combination of a CS/DS (Code Storage/Data Storage) being a system memory on the side of the CPU, and a cache (Cache) memory.
As shown in FIG. 21, with dual write of data in the first previous example, firstly, data is written into the battery-backed-up memory 201 being a combination of a CS/DS and a cache from the front-end chip (FE) 204 via the memory control hub (MCH) 203. Secondly, the data written into the memory 201 is read into the Central Processing Unit (CPU) 202 via the memory control hub (MCH) 203, and a copy process is executed for dual writing of data in the Central Processing Unit (CPU) 202. Thirdly, dual write of data is performed to any other system using a dual path (Dual Path) of the Peripheral Component Interconnect Express (PCIe) 209 from the Central Processing Unit (CPU) 202 via the memory control hub (MCH) 203.